Roll No													

Presidency University 
Bengaluru
 
 SCHOOL OF ENGINEERING
SUMMER TERM END TERM EXAMINATION - AUGUST 2024 

Date: 05-08-2024
Time: 01:00 PM – 04:00 PM
Max Marks: 100
Weightage:  50%

Semester: Summer Term (B.Tech)
Course Code: ECE3050
Course Name: Design for Testability
Department: Electronics & Communication Engineering

 

          Instructions:
(i)	Read the all questions carefully and answer accordingly. 
(ii)	Do not write any matter on the question paper other than roll number.

PART A
Answer any 5 Questions. Each question carries 2 marks.                (5Qx 2M= 10M) 
1 Test engineers usually have to construct test vectors after the design is completed. Integration of design and test, referred to as design for testability (DFT), was proposed in the 1970s. List out the Categories of DFT techniques?
(CO 1) [Knowledge]
2 In general, topology-based testability analysis, such as SCOAP or probability-based testability analysis, is computationally efficient but can produce inaccurate results for circuits containing many reconvergent fanouts.What are the 3 numerical values available for a signal in a combinational circuit for SCOAP analysis? 
(CO 2) [Knowledge]
3. Singular cover is the compact form of truth table. Write the singular cover for 2 input AND Gate?
(CO 3) [Knowledge]
4. Name two test vector generation techniques for detecting only single faults but not multiple faults?
(CO 3) [Knowledge]

5. BIST identifies defects during manufacturing, preventing faulty chips from reaching consumers and ensuring only high-quality, reliable chips reach the market. What are the different ways that online BIST can be carried out?
(CO 4) [Knowledge]
6. Signature analysis along with scan path is used in BILBO. List out the modes in BILBO?
(CO 4) [Knowledge]
7. An automated test pattern generator called Built-in Self-Test is utilized to find faults. Draw the block diagram for logic BIST system?
(CO 4) [Knowledge]

PART B
Answer any 5 Questions. Each question carries 10 marks.	           (5Qx 10M= 50M) 

8 Generate a minimum set of test vectors to detect all single stuck-at faults for a cascade of     full adder in an n-bit ripple carry adder. How many test vectors are needed?
(CO 1) [Comprehension]
9 The VLSI design process is essentially a process of transforming a higher level description of a design to a lower level description. Once verified, the VLSI design then goes to fabrication. Explain different levels of abstraction in VLSI design verification?
(CO 1) [Comprehension]
10 What are the SCOAP Combinational Controllability Calculation Rules for 1-Controllability (Primary Input, Output, Branch) of AND, OR, NOT gates. Calculate the SCOAP based Combinational Controllability and Observability measures for the following circuit?
(CO 2) [Comprehension]

11 What are the Probability based Controllability Calculation Rules for 0-Controllability (Primary Input, Output, Branch) of AND, OR, NOT gates. Calculate the Probabil
(CO 2) [Comprehension]

12 Scan design, the most widely used structured DFT methodology, attempts to improve testability of a circuit by improving the controllability and observability of storage elements in a sequential design. Typically, this is accomplished by converting the sequential design into a scan design with different modes of operations. Explain about Edge triggered Muxed D Scan Cell design and operation with suitable diagrams and waveforms?
(CO 2) [Comprehension]
13 Write the equations for testing SA0 and SA1 fault on line Xi of function f(x) using boolean difference method? Generate the test vector for finding SA0 fault on line x1 of the following figure using Boolean difference method with all simplification steps to be mentioned?
(CO 3) [Comprehension]

14. Prove that two faults, f and g, in a combinational circuit with the same PDCF faults that has at least one D or compliment of D, can be propagated to a primary output the same way.
(CO 3) [Comprehension]
PART C
Answer any 2 Questions. Each question carries 20 marks.             (2Qx 20M= 40M) 
15. 
A) The number of failures in 10 power 9 hours is a unit (abbreviated FITS) that is often used in reliability calculations. There is a system with 200 components where each component has a failure rate of 1000 FITS, yield is 60% with fault coverage as 20% and system availability as 99.999%. Calculate the overall failure rate, MTBF, MTTR, repair rate, and defect level, for this system with necessary formulas?
B) At the switch level, a transistor can be stuck open or stuck short. These fault models cannot accurately reflect the behaviour of faults in CMOS logic circuits because of multiple transistors used.  Illustrate the concept of above stuck faults in 2 input CMOS NAND gate with the help of truth table and explanation?
(CO 1) [Application]
16. 
A) Explain the steps in D algorithm? Generate the test vector for SA0 fault on the line f as shown in figure?
(CO 3) [Application]

B) Draw the D intersection table of above D Algorithm?
C) Generate the test vector for a-tests for the following function?
f= x1x2+x1x3x4+x2x4

17. 
A) Write a detail description about LFSR types and properties with a neat sketch? Generate the test sequence for both types using an example?
B) Write about serial signature analysis with a neat sketch and generate the signature table for faulty and fault free circuit?
(CO 4) [Application]